A High Noise Immunity, 28 × 16-Channel Finger Touch Sensing IC Using OFDM and Frequency Translation Technique

In this paper, a high noise immunity, 28 × 16-channel finger touch sensing IC for an orthogonal frequency division multiplexing (OFDM) touch sensing scheme is presented. In order to increase the signal-to-noise ratio (SNR), the OFDM sensing scheme is proposed. The transmitter (TX) transmits the orthogonal signal to each channels of the panel. The receiver (RX) detects the magnitude of the orthogonal frequency to be transmitted from the TX. Due to the orthogonal characteristics, it is robust to narrowband interference and noise. Therefore, the SNR can be improved. In order to reduce the noise effect of low frequencies, a mixer and high-pass filter are proposed as well. After the noise is filtered, the touch SNR attained is 60 dB, from 20 dB before the noise is filtered. The advantage of the proposed OFDM sensing scheme is its ability to detect channels of the panel simultaneously with the use of multiple carriers. To satisfy the linearity of the signal in the OFDM system, a high-linearity mixer and a rail-to-rail amplifier in the TX driver are designed. The proposed design is implemented in 90 nm CMOS process. The SNR is approximately 60 dB. The area is 13.6 mm2, and the power consumption is 62.4 mW

A 10- and 12-Bit Multi-Channel Hybrid Type Successive Approximation Register Analog-to-Digital Converter for Wireless Power Transfer System

This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) designed for a wireless power transfer system. This is a four–channel SAR ADC structure with 10-bit resolution for each channel, which can also be applied as a single 12-bit ADC. To reduce the area and the number of the required devices in the ADC module, a hybrid-type structure with capacitor and resistor DACs is applied, in which the resistor DAC is shared between channels and determines the seven least significant bits (LSB)s, while the capacitor DAC determines the three most significant bits (MSBs). For the 12-bit operation mode, and to reduce the number of capacitors required in the capacitor DAC, the capacitors of the four channels are shared to determine the five MSBs. A foreground calibration is applied to the capacitor DAC to remedy the gain and offset errors after fabrication. An additional low resistive path is also implemented in the resistor DAC for error correction. The conversion speed for 10- and 12-bit operations reaches up to 1 and 0.5 MS/s, respectively. The prototype ADC is designed in a 180 nm complementary metal-oxide semiconductor (CMOS) process. For 10- and 12-bit operating modes, this ADC module achieves up to 9.71 and 11.76 effective number of bits (ENOBs), respectively

Design of a 900 MHz dual-mode SWIPT for low-power IoT devices

This paper presents a duty cycle-based, dual-mode simultaneous wireless information and power transceiver (SWIPT) for Internet of Things (IoT) devices in which a sensor node monitors the received power and adaptively controls the single-tone or multitone communication mode. An adaptive power-splitting (PS) ratio control scheme distributes the received radio frequency (RF) energy between the energy harvesting (EH) path and the information decoding (ID) path. The proposed SWIPT enables the self-powering of an ID transceiver above 20 dBm input power, leading to a battery-free network. The optimized PS ratio of 0.44 enables it to provide sufficient harvested energy for self-powering and energy-neutral operation of the ID transceiver. The ID transceiver can demodulate the amplitude-shift keying (ASK) and the binary phase-shift keying (BPSK) signals. Moreover, for low-input power level, a peak-to-average power ratio (PAPR) scheme based on multitone is also proposed for demodulation of the information-carrying RF signals. Due to the limited power, information is transmitted in uplink by backscatter modulation instead of RF signaling. To validate our proposed SWIPT architecture, a SWIPT printed circuit board (PCB) was designed with a multitone SWIPT board at 900 MHz. The demodulation of multitone by PAPR was verified separately on the PCB. Results showed the measured sensitivity of the SWIPT to be −7 dBm, and the measured peak power efficiency of the RF energy harvester was 69% at 20 dBm input power level. The power consumption of the injection-locked oscillator (ILO)-based phase detection path was 13.6 mW, and it could be supplied from the EH path when the input power level was high. The ID path could demodulate 4-ASK- and BPSK-modulated signals at the same time, thus receiving 3 bits from the demodulation process. Maximum data rate of 4 Mbps was achieved in the measurement

A Design of Small Area, 0.95 mW, 612–1152 MHz Open Loop Injection-Locked Frequency Multiplier for IoT Sensor Applications

This paper presents a 612–1152 MHz Injection-Locked Frequency Multiplier (ILFM). The proposed ILFM is used to send an input signal to a receiver in only the I/Q mismatch calibration mode. Adopting a Phase-Locked Loop (PLL) to calibrate the receiver places a burden on this system because of the additional area and power consumption that is required. Instead of the PLL, to satisfy high-frequency, low-jitter and low-area requirements, a Ring Oscillator is adopted in the system. The free-running frequency of the ILFM is automatically and digitally calibrated to reflect the frequency of the injected signal from the harmonics of the reference clock. To control the frequency of the ILFM, the load current is digitally tuned with a 6-bit digital control signal. The proposed ILFM locks to the target frequency using a digitally controlled Frequency Locked Loop (FLL). This chip is fabricated using 1-poly 6-metal 0.18 µm CMOS and has achieved the wide tuning range of 612–1152 MHz. The power consumption is 0.95 mW from a supply voltage of 1.8 V. The measured phase noise of the ILFM is −108 dBc/Hz at a 1 MHz offset

A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm2. With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply